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Google Advanced Process Node Foundry Interface Engineer, Silicon in New Taipei City, Taiwan

Google welcomes people with disabilities.

Minimum qualifications:

  • Bachelor's degree in Electrical Engineering, Mechanical Engineering, Materials Science, Chemical Engineering, a related field, or equivalent practical experience.

  • 5 years of experience with vendor management, product packaging development, new product introduction, and mass volume production.

  • Experience with CMOS device/integration and yield analysis.

Preferred qualifications:

  • Master's degree or PhD in Electrical Engineering, Mechanical Engineering, Materials Science, Chemical Engineering, related degree or equivalent practical experience.

  • Experience with drive foundry identifying yield detractors, finding recipes to improve yield, and demonstrating/validating via DOEs.

  • Experience in yield analysis, yield pareto, and root cause analysis through diagnostic tools (e.g., Synopsys Yield Explorer tools).

Our computational challenges are so big, complex and unique we can't just purchase off-the-shelf hardware, we've got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google's services. As a Hardware Engineer, you design and build the systems that are the heart of the world's largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.

As the Advanced Process Node Foundry Interface Engineer, you will be responsible for driving Complementary Metal Oxide Semiconductor (CMOS) foundry partners, tracking design kits, design collaterals development, assess technology risks, and work on test chips. You will support IP, Chip Design, and Implementation teams on planning and performing CMOS scaling, Power Performance Area (PPA) analysis, and producing technology roadmap benchmarks.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

  • Work with foundry partners on optimization of transistor (e.g., Logic, SRAM, IOs) performance/goals on advanced CMOS technology platforms, and meeting Google product performance and power requirements.

  • Drive Foundry partners for competitive PDK enablement, work with them to enhance Model accuracy by matching Silicon and optimize process to support product Fmax/Power KPI/Yield.

  • Drive root-cause debug activities from process/yield issues, come up with solutions, and estimate impact on productization.

  • Lead model to silicon verification through multiple test vehicles, and help bring products to market with entitlement yield.

Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also https://careers.google.com/eeo/ and https://careers.google.com/jobs/dist/legal/OFCCPEEOPost.pdf If you have a need that requires accommodation, please let us know by completing our Accommodations for Applicants form: https://goo.gl/forms/aBt6Pu71i1kzpLHe2.

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